Topic 2
3.2 CPU
3.2 CPU learning objectives and workbook content.
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Topic
Paper progress
Paper 1
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Paper 2
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Paper 3
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Learning path by learning objective
12.3.2.1
Paper 1
describe the RISC architecture
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
12.3.2.2
Paper 1
describe the CISC architecture
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
12.3.2.3
Paper 1
compare RISC and CISC
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
12.3.2.4
Paper 1
explain how data are transferred between the components of a computer system through the address bus, data bus and control bus
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
12.3.2.5
Paper 1
explain the instruction cycle (fetch / decode / execute)
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
12.3.2.6
Paper 1
explain how the clock rate, word length and bus width affect the CPU performance
Theory
No theory linked to this LO yet.
Workbook
No workbook tasks linked to this LO yet.
Glossary
No glossary terms added yet.